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Conference Papers Year : 2024

A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking

Abstract

Cache-based timing side-channel attacks are prevalent and correspond to a security threat for both high-end and embedded processors. In this paper, we propose and implement a fine-grained dynamic partitioning countermeasure relying on a hardware-software collaboration. The proposed approach extends the RISC-V Instruction Set Architecture (ISA) with lock and unlock instructions to allow a program to explicitly lock cache lines in the data cache memory, ensuring constant-time accesses. Experimental results show that the proposed solution defeats contention-based cache side-channel attacks such as PRIME+PROBE and leads to a low area overhead (<3%), a low impact on binary code size (<0.3%) and a low impact on miss rate (<2%).
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Dates and versions

hal-04619896 , version 1 (21-06-2024)

Identifiers

  • HAL Id : hal-04619896 , version 1

Cite

Nicolas Gaudin, Pascal Cotret, Gogniat Guy, Vianney Lapotre. A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking. 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2024), Jul 2024, Knoxville, TN, United States. ⟨hal-04619896⟩
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